Jamie Iles

www.jamieiles.com | github.com/jamieiles | uk.linkedin.com/in/jamieiles




C, C++, Python, Lua, ASM, Bash, SystemVerilog


GNU toolchain, Git, Jenkins, CMake, Lauterbach Trace32, GoogleTest and GoogleMock, OpenEmbedded, qemu, ARM Fast Models, MySQL, Ansible, Docker, AFL, KiCad


x86, ARMv7/ARMv8, RISC-V


Linux kernel, GNU/Linux (rpm/deb/embedded), Zephyr RTOS, Arm TF-A, EDK2, bare metal


Quartus+Vivado FPGA tools, PCIe, Icarus Verilog, Verilator, Logic Analyzers, Oscilloscopes, JTAG, Kicad PCB design, PCB assembly


Computer systems engineer and technical leader with over 17 years proven semiconductor industry experience with a focus on low-level and systems software including pre-silicon, hardware development, security, bringup, kernel development, libraries and development tools. I have broad experience in the software life-cycle from planning through to execution and leading large and productive global engineering teams.

My specialities include software security, pre-silicon development and hardware bringup, technical leadership, Linux OS development (kernel + userspace), hardware/software co-design, C, C++, Python.


Principal Engineer

April 2020 - present

Software enablement for custom CPUs at Qualcomm. After joining Nuvia Inc in April 2020, we were acquired by Qualcomm in March 2021. My main responsibilities include pre-silicon OS bringup and development for high performance custom CPUs, exploration of future architectural evolutions, virtual platform modelling and firmware development. I was the previously Operating Systems lead for the Nuvia server SoC.

  • Validation of ARMv8 CPU and SoC architectural features in a pre-silicon environment. Responsible for initial OS bringup and debug on new pre-silicon CPU designs. Focus areas include power+performance management and quality-of-service (MPAM), debugging Linux boot and runtime issues in emulation, prototype and silicon environments.
  • Upstream Linux kernel development and verification.
  • Application processor firmware development (TF-A+EDK2) for pre-silicon enablement.
  • Built a whole system test suite in Python to fully automate the exercise of designs in pre-silicon emulation with support for pre-loaded PMEM ramdisks, and EFI variable based configuration running high level OS based workloads.
  • Enhancements to qemu hardware models and code generator to model new platforms, CPU extensions, diagnostic+performance tracing of CPU execution and bug fixes.
  • Enhancements to platform firmware adding fuzzing of bootrom and runtime microcontroller firmware with AFL; Zephyr bug fixes for MMU+MPU handling, stack canaries, AArch32 cache maintenance; and implementing cache maintenance for microcontroller IPC.
  • Development of ACPI firmware/operating system interfaces for OSPM services including power and performance management, platform notifications and PCC design.
  • Added Linux support for ACPI based enumeration of I3C controllers and dynamic I2C peripherals.
  • Designing mitigations for security side channels; next generation SOC+CPU features and design review for CPU+SOC architecture, errata and workaround development.
  • Automation of CI infrastructure configuration with Ansible, development of GitLab CI pipelines.
  • Developed minimized Ubuntu based Linux images and boot processes for fast boot in emulation environments with minimal I/O devices.

Software Development Director

January 2012 - April 2020

Head of engineering for the Ksplice team, providing rebootless updates for Linux operating systems, reporting to the VP of Linux and Virtualisation. I joined the team in January 2012 as a Senior Developer before leading the team responsible for releasing over 200,000 rebootless updates per year for security fixes to customers with critical systems.

  • Leading a global, remote team of 18 engineers, including hiring.
  • Development of the Ksplice core technology in both the C/C++ tools and kernel modules including support for new kernel versions, compatibility with DTrace for Linux, enhanced debugging and new patching features.
  • Developed proof-of-concept reproducers for CPU side-channel vulnerabilities including Meltdown+L1 Terminal Fault and made recommendations for Oracle's OS mitigation response.
  • Analysis of kernel security vulnerabilities, developing reproducers and live patches to fix the vulnerability.
  • Led the engineering of Ksplice for user-space processes on Oracle Linux from proof-of-concept to production. Implemented the Ksplice core to analyze ELF object files and running processes on Linux using C++, Boost, Python, ptrace, GoogleTest+GoogleMock. This work enabled Oracle Linux to be the only Linux distribution capable of live-patching user-space for high profile vulnerabilities such as DROWN, and glibc CVE-2015-7547 (DNS stack buffer overflow).
  • Developed a Python based regression test suite for the Ksplice tools and new Python based tools for Ksplice update production and analysis.
  • Migrated the software stack to Oracle technologies based on Oracle Linux 6.
  • Championing modern software development techniques including Test Driven Development throughout the team.

Embedded Software Engineer

October 2011 - January 2012

Development of security testing framework including secure communications and embedded Linux hardening guidelines.

Principal Software Engineer

June 2006 - September 2011

  • Ported Linux to three ARM1176JZ-S based SoC devices (picoxcell) with drivers for cryptographic offload, the picoArray DSP, One Time Programmable memory, eFuses, clock gating and power management and assisted in hardware bringup and silicon validation. This included work with the Open Source Community to include Picochip code into upstream projects.
  • Development of an bare-metal ARM application to enable high-throughput and low latency communications between the picoArray DSP and a remote host over a raw Ethernet link.
  • Development of a secure hypervisor utilizing ARM TrustZone providing secure services to a Linux system.
  • Design and implementation of Linux APIs and applications to enable communication with Picochip peripherals including an intelligent debug server.
  • Replaced the proprietary BSP build system with OpenEmbedded to produce a scalable build system and reduce the porting effort for customer boards.
  • Implemented an automated regression system for testing of the BSP and hardware platforms.
  • Optimization of cryptographic services for femtocell stack software, decreased CPU utilization of ciphering by 30%.
  • Promoted the use of Open Source Software within Picochip and the development of an Open Source Policy.

Professional Qualifications

I am a Chartered Engineer, registered with the Institution of Engineering and Technology in August 2016.


University of Bristol

2002 - 2006

First Class MEng (Hons), Computer Systems Engineering

Final year project produced an application to automatically generate parameters for an audio parametric equaliser using cepstrum analysis and genetic algorithms based on a sample audio source for home studios. Units undertaken included advanced computer architecture, mobile and ubiquitous systems, information security and cryptography.

Other projects


June 2019 - present

I have implemented an RV32IMA RISC-V core in SystemVerilog that offers ~2.61 CoreMark/MHz. The core implements the privileged architecture with SSTC and Sscofpmf extensions and runs mainline Linux. I implemented a number unique tracing techniques to record and replay execution to generate ELF core-files for software debug. The core is a scalar design with parallel execution units and out of order completion, register rename and dynamic branch prediction. The system runs on a Spartan 7 FPGA and has been hardened with OpenLane for the SKY130A process. I upstreamed fixes to the Linux kernel to enable ftrace on RV32.

80186 Compatible CPU

May 2016 - present

I implemented a very compact microcoded Intel X86 (80186) binary compatible processor core in SystemVerilog, unit testing with Verilator and GoogleTest, an FPGA based reference design and C BIOS that runs unmodified MS-DOS, FreeDOS and others. The CPU implements the full 80186 programmers model, adding JTAG for remote debug. The System-on-chip has a VGA controller, cache, timers, interrupt controller and PS/2 controllers. I built two custom 4-layer PCBs using fine-pitch BGA+QFP components and an Intel MAX 10 as a development platform along with an Intel 8088 pin compatible FPGA module.

Oldland CPU

April 2013 - April 2015

I created the Oldland CPU, a custom, 32-bit RISC soft CPU in Verilog that runs on an FPGA. This is a full featured SoC and includes TLBs, caches, privilege modes, and a number of peripherals including an SPI controller, programmable interrupt controller, timers, GPIO and UART. I ported GNU binutils+gcc, u-boot and the RTEMS RTOS to this architecture.

Hobbies and Interests

I enjoy triathlon, playing blues and rock guitar, and learning hardware design with FPGAs.